1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an internal ground potential boosted from an external ground potential.
2. Description of the Background Art
FIG. 6 illustrates a circuit diagram showing the structure of the main portion of a dynamic random access memory (DRAM). Referring to FIG. 6, the DRAM includes a memory cell MC connected to a bit line BL and to a word line WL, and memory cell MC includes a capacitor Cs and a transistor Q. When data is written to memory cell MC, according to the data, bit line BL is applied with "H" (high) level (power supply potential Vcc) or "L" (low) level (ground potential GND) and word line WL is applied with "H" level so that transistor Q is rendered conductive, thereby charging capacitor Cs. When reading data from memory cell MC, after rendering bit line BL floating by applying a predetermined potential (for example, Vcc/2) to bit line BL, word line WL is changed to "H" level so that transistor Q is rendered conductive, and a slight change in potential of bit line BL is amplified to "H" or "L" level for reading data. Thus, in a DRAM, memory cell MC can be rewritten and data written in the memory cell MC can be read freely.
However, for a conventional DRAM, since the "L" level of amplitude of bit line BL is the ground potential GND which is the same as the "L" level of an unselected word line WL, a sub-threshold leak current Is which leaks from capacitor Cs into bit line BL via transistor Q is relatively large. Therefore, the conventional DRAM has a problem that data written into memory cell MC will disappear in a relatively short period of time.
Accordingly, the inventors of the present invention have proposed pseudo GND method in which the "L" level of bit line BL is adapted to be a pseudo GND potential BSG, which is higher than the "L" level of word line WL, that is, the ground potential GND.
FIG. 7 illustrates a partially omitted circuit diagram of a DRAM to which the pseudo GND method is applied. Referring to FIG. 7, the DRAM includes a power supply line 31 through which the power supply potential Vcc is externally provided, a ground line 32 through which the ground potential GND is externally provided and a pseudo GND line 33 the level of which is maintained to the pseudo GND potential BSG, which is higher than the ground potential GND.
Furthermore, the DRAM includes an internal circuit 34, a reference potential generating circuit 35, a differential amplifier 36 and an n-channel MOS transistor 37. The internal circuit 34 is a circuit associated with determining the potential of bit line BL such as a charging and discharging circuit (a sense amplifier circuit) for a bit line or a Vcc/2 generating circuit, and is not the entire circuit within the chip (especially, a word line drive circuit is not included in the internal circuit 45). For a conventional DRAM, the internal circuit 34 is connected between the power supply line 31 and the ground line 32. For the DRAM of the pseudo GND method, the internal circuit is connected between the power supply line 31 and the pseudo GND line 33.
The reference potential generating circuit 35 includes a constant current source 38 and a resistor 39 which are connected in series between the power supply line 31 and the ground line 32, as shown in FIG. 8. When a constant amount of current is supplied from the constant current source 38, a reference voltage Vref, which is of the value of the current multiplied by the resistance of resistor 39, is output at the connecting node N38 between the constant current source 38 and resistor 39.
Referring to FIG. 9, the differential amplifier 36 includes p-channel MOS transistors 40, 41 and n-channel MOS transistors 42, 43. MOS transistors 40, 42 are connected in series between the power supply line 31 and the ground line 32. M0S transistors 41, 43 are connected in series and they are also connected in parallel with MOS transistors 40, 42. The gates of MOS transistors 40, 41 are connected to a connecting node N40 of MOS transistors 40 and 42. The gate of MOS transistor 42 is connected to the pseudo GND line 33. The gate of MOS transistor 43 is supplied with the reference potential Vref from the reference potential generating circuit 35. A connecting node N41 of MOS transistors 41 and 43 is the output node of the differential amplifier 36.
Through MOS transistor 42, a current Id flow according to the potential of the pseudo GND line 33. Through MOS transistor 43, a constant amount of current Ie flow according to the reference potential Vref. Since MOS transistors 42 and 40 are connected in series and MOS transistors 40 and 41 configure a current mirror circuit, the same current Id flow through the three MOS transistors 40, 41, 42.
Therefore, when the potential of the pseudo GND line 33 is higher than the reference potential Vref and current Id is larger than current Ie, then subtracting current Ie from Id gives a positive value and node N41 will be pulled up to "H" level. On the other hand, when the potential of the pseudo GND line 33 is lower than the reference potential Vref and current Id is smaller than current Ie, subtracting current Ie from Id gives a negative value and node N41 will be pulled down to "L" level.
Furthermore, n-channel MOS transistor 37 is connected between the pseudo GND line 33 and the ground line 32, and its gate receives the output Vout of the differential amplifier 36.
The operation of the circuit shown in FIG. 7 will now be described. The current supplied from the power supply line 31 to the internal circuit 34 drives the internal circuit 34 and then flow into the pseudo GND line 33. When the potential of the pseudo GND line 33 goes higher than the reference potential Vref, the differential amplifier 36 will output "H" level so that MOS transistor 37 can be conducted. On the other hand, when the potential of the pseudo GND line 33 goes lower than the reference potential Vref, the differential amplifier 36 will output "L" level so that MOS transistor 37 cannot be conducted. Thus, the potential of the pseudo GND line 33 is maintained to the pseudo GND potential BSG, which is nearly equal to the reference potential Vref.
FIG. 10 is a partially omitted circuit diagram illustrating the configuration of another DRAM to which the pseudo GND method is applied. Referring to FIG. 10, this DRAM differs from the DRAMs shown in FIGS. 7-9 in that an n-channel MOS transistor 44 is connected between the sources of MOS transistors 42, 43 in the differential amplifier 36 and the ground line 32. The gate of n-channel MOS transistor 44 receives a signal .phi.s for activating the internal circuit shown in FIG. 7.
During a stand-by period of the internal circuit 34, the activating signal .phi.s is at "L" level and MOS transistor 44 may be shut down. Therefore, the differential amplifier 36 is deactivated. During an active period of the internal circuit 34, the activating signal .phi.s is at "H" level and MOS transistor 44 may be conducted. Therefore, the differential amplifier 36 is activated. The operation of this DRAM during the active period is the same as those of the DRAMs shown in FIGS. 7-9.
In this DRAM, the differential amplifier 36 can be deactivated during a stand-by period of the internal circuit 34, thereby reducing power consumption.
FIG. 11 is a partially omitted block diagram of a circuit illustrating the configuration of still another DRAM to which the pseudo GND method is applied. Referring to FIG. 11, this DRAM differs from the DRAM shown in FIG. 7 in that a diode 45 is connected between the pseudo GND line 33 and the drain of n-channel MOS transistor 37.
For this DRAM, the difference of potential between the pseudo GND line 33 and the ground line 32 will never be smaller than a threshold voltage of diode 45. Thus, the potential drop of the GND line 33 due to a delay in the response by the differential amplifier 36 can be prevented.
FIG. 12 is a partially omitted block diagram of a circuit illustrating the configuration of still another DRAM to which the pseudo GND method is applied. Referring to FIG. 12, this DRAM differs from the DRAM shown in FIG. 11 in that a decoupling capacitor 46 is connected in parallel with n-channel MOS transistor 37.
For this DRAM, capacitor 46 can prevent the potential of the pseudo GND line 33 from rapidly changing, so that a stable pseudo GND potential BSG can be obtained.
FIG. 13 is a partially omitted block diagram of a circuit illustrating the configuration of still another DRAM to which the pseudo GND method is applied. Referring to FIG. 13, this DRAM differs from the DRAM shown in FIG. 7 in that n-channel MOS transistors 47, 48 and a sustain circuit 49 are further provided in the DRAM.
The drain and gate of n-channel MOS transistor 47 are connected to the pseudo GND line 33, and its source is connected to the ground line 32. During a stand-by period of the internal circuit 34, n-channel MOS transistor 47 will maintain the pseudo GND line 33 to a threshold voltage Vth of n-channel MOS transistor 47.
N-channel MOS transistor 48 is connected between the pseudo GND line 33 and the ground line 32, and its gate receives a signal .phi.s which is synchronized with a sense amplifier-activating signal. The signal .phi.s will go to "H" level at the time the sense amplifier operates where a large amount of current flows into the pseudo GND line 33 from the internal circuit 34 including the sense amplifier, so that n-channel MOS transistor 48 is rendered conductive, thereby flowing the large amount of current from the internal circuit out into the ground line 32.
The sustain circuit 49 includes an oscillator 50 and a pumping circuit 51. The pumping circuit 51 intermittently supplies electric charges to the pseudo GND line 33 in response to an oscillation signal from the oscillator 50. Accordingly, the potential of the pseudo GND line 33, even if going lower than the pseudo GND potential BSG, can be quickly returned to BSG.
In this DRAM, the combination of these components allow for a more stable pseudo GND potential BSG.
For the DRAMs shown in FIGS. 7-13 to which the pseudo GND method is applied, however, the reference potential generating circuit must be included and this causes problems such as a more complex circuit configuration and a larger amount of power consumption.